Intel frigiver Compute Express Link (CXL) 1.0, ny interconnect-protokol, der muliggør PCIe gen 5.0



Intel has been working on CXL, short for Compute Express Link gen 1, for over four years new. This new interconnect protocol was donated to a new consortium of tech companies for release as a the CXL 1.0 standard. Its protocol layer will pave the way for PCI-Express gen 5.0 to sustain its bandwidth growth target of being twice as fast as PCIe gen 4.0. CXL 1.0 is out to compete with other established PCIe-alternative slot standards such as NVLink from NVIDIA, and InfinityFabric from AMD. It has one killer advantage, though: the CXL 1.0 is pin-compatible and backwards-compatible with PCI-Express, and uses PCIe physical-layer and electrical interface.

Dette reducerer omkostninger til hardwareopgradering for datacentre. CXL opretholder hukommelseskoherensen mellem CPU's hukommelsesrum og hukommelse på installerede enheder. CXL Consortium eller SIG inkluderer datacentre og cloud computing-giganter, herunder Alibaba, Cisco, DellEMC, Facebook, Google, HPE, Huawei, Microsoft og naturligvis Intel. CXL bruges bot som en socket / slids interface til add-on kort og GPU boards og som en integreret interface. Vi estimerer båndbredde for CXL til at være 32 Gbps pr. Bane eller fire gange så stor som PCIe gen 3.0, hvilket holder i overensstemmelse med PCIe gen 5.0 båndbreddevækstestimater.
Source: AnandTech